A Novel Technique to Mitigate the Overlap-Time Effect in Current Source Inverters

Abstract

Generally, the current source inverter is considered more reliable than the voltage source inverter due to the presence of inductor as an energy storage element on the DC link, but a disruption in the inductor current could significantly risk its reliability. To guarantee the reliable operation of current source inverter, an overlap time must be added to the gate signals of its switches. This ensures the safe operation of current source inverter but results in increased total harmonic distortion and reduction of DC current utilization ratio. This paper proposes a new technique for reducing the effect of overlap time and improving the performance of pulse width modulated current source inverter. The proposed technique modifies the level-shifted sinusoidal pulse width modulation to mitigate the effect of overlap time. In this paper, the working principle of the proposed technique is presented in detail, and a mathematical relation between the level shifting and overlap time is established. Moreover, a function for the approximation of output AC current is also presented. Finally, results from computer simulations and experiments are presented which validate the effectiveness of the proposed technique.